
IDT709279/69S/L
High-Speed 32/16K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance (1)
t CYC2
CLK
t CH2
t CL2
t SA
t HA
ADDRESS
ADS
CNTEN
An
t SAD t HAD
t CD2
t SAD t HAD
t SCN t HCN
DATA OUT
Qx - 1 (2)
Qx
Qn
Qn + 1
Qn + 2 (2)
Qn + 3
t DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
3243 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance (1)
t CYC1
CLK
t CH1
t CL1
t SA
t HA
ADDRESS
ADS
An
t SAD t HAD
t SAD t HAD
t SCN t HCN
CNTEN
t CD1
DATA OUT
Qx (2)
Qn
Qn + 1
Qn + 2
Qn + 3 (2)
Qn + 4
t DC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
3243 drw 16
NOTES:
1. CE 0 , OE , UB , and LB = V IL ; CE 1 , R/ W , and CNTRST = V IH .
2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = V IL (advancing the address), i.e. ADS = V IH and CNTEN = V IH , then the data
output remains constant for subsequent clocks.
14
6.42